PXE's internal process engine, which forms the basis for BPEL process execution, is based on a unique virtual processing unit or "VPU". The VPU is designed specifically to model and execute processes defined by message passing, and it operates on process expressions that represent a process as a combination of its capabilities for communication and evolution over time.

To execute a process defined in BPEL, PXE uses a compiler to turn the BPEL process definition into a process expression with some accompanying metadata. See [Compiler Toolchain] for more information about the compiler.

The compiled process expression will bear a strong resemblance to the original BPEL process in terms of external communication, but the process expression will also contain the internal communications that the compiler uses model the semantics of the BPEL process such as a <sequence> or <flow>. This is analogous to a Java compiler that produces Java byte code as input for the Java virtual machine or a C compiler that produces object code for a physical CPU. This design has a number of advantages over more direct approaches:

• The VPU is not limited to a particular version of BPEL, a language that deals with web services interactions, or even a specific family of process language specifications; the same VPU core can simultaneously execute any combination of processes compiled from different process definition languages.

• The VPU does not use native constructs to model orchestration constructs. For example, the separate "threads" in a BPEL <flow> are not represented by native Java threads.

• The VPU is fundamentally asynchronous.

At runtime, the VPU operates in a reactive mode in that it pairs a message with a process expression waiting to receive it. The VPU then reduces the process expression, producing a (potentially empty) set of messages to be sent and a new (also potentially empty and thus completed) process expression; this is analogous to substituting a value into a complex algebraic expression and then simplifying. The reduction loop is depicted in the figure above.